library ieee;
use ieee.numeric_std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.dec_pkg.all;



entity convnoise is
port(
      clk: in std_ulogic; 
      flag: in std_ulogic;
		flag1: in std_ulogic;
		z0_w:in matrix_23_23;
		z1_w:in matrix_23_23;
		p_w:in matrix_23_20;
	s_w: out std_ulogic_vector(15 downto 0)
		-- res:out std_ulogic_vector(20 downto 0)
		--t0_w,t1_w: out std_ulogic_vector(20 downto 0)
		);
end convnoise;

architecture beh of convnoise is

signal d0_w,d1_w:matrix_23_24;
signal s0,s1:matrix_29_24;
signal d012,d013,d014,d015,d016,d017,d018,d019,d020,d021,d022,d112,d113,d114,d115,d116,d117,d118,d119,d120,d121,d122,d0222,d1222,s019,s119: std_ulogic_vector(23 downto 0);
signal t0_w,t1_w: std_ulogic_vector(23 downto 0);
signal counter:std_ulogic_vector(3 downto 0);
--signal flag_f:std_logic :='0';

component  max2clk_24 is
port(
      clk: in std_ulogic;
		  x1,x2: in std_ulogic_vector(23 downto 0);
		  y:out std_ulogic_vector(23 downto 0)
	);
end component;

begin


process(clk,p_w(0 to 22),z0_w(0 to 22),z1_w(0 to 22),flag1)
  
begin
  if flag1 = '1' then 
   if clk'event and clk='1'  then
  for i in 0 to 22 loop
    d0_w(i)<=usxt(p_w(i),24)-usxt(z0_w(i),24);
		d1_w(i)<=usxt(p_w(i),24)-usxt(z1_w(i),24);
 end loop;
 end if;
 end if;
--     d0_w(0)<=usxt(p_w(0),21)-usxt(z0_w(0),21);
--   d0_w(1)<=usxt(p_w(1),21)-usxt(z0_w(1),21);
--   d0_w(2)<=usxt(p_w(2),21)-usxt(z0_w(2),21);
--   d0_w(3)<=usxt(p_w(3),21)-usxt(z0_w(3),21);
--   d0_w(4)<=usxt(p_w(4),21)-usxt(z0_w(4),21);
--   d0_w(5)<=usxt(p_w(5),21)-usxt(z0_w(5),21);
--   d0_w(6)<=usxt(p_w(6),21)-usxt(z0_w(6),21);
--   d0_w(7)<=usxt(p_w(7),21)-usxt(z0_w(7),21);
--   d0_w(8)<=usxt(p_w(8),21)-usxt(z0_w(8),21);
--   d0_w(9)<=usxt(p_w(9),21)-usxt(z0_w(9),21);
--   d0_w(10)<=usxt(p_w(10),21)-usxt(z0_w(10),21);
--   d0_w(11)<=usxt(p_w(11),21)-usxt(z0_w(11),21);
--   d0_w(12)<=usxt(p_w(12),21)-usxt(z0_w(12),21);
--   d0_w(13)<=usxt(p_w(13),21)-usxt(z0_w(13),21);
--   d0_w(14)<=usxt(p_w(14),21)-usxt(z0_w(14),21);
--   d0_w(15)<=usxt(p_w(15),21)-usxt(z0_w(15),21);
--   d0_w(16)<=usxt(p_w(16),21)-usxt(z0_w(16),21);
--   d0_w(17)<=usxt(p_w(17),21)-usxt(z0_w(17),21);
--   d0_w(18)<=usxt(p_w(18),21)-usxt(z0_w(18),21);
--   d0_w(19)<=usxt(p_w(19),21)-usxt(z0_w(19),21);
--   d0_w(20)<=usxt(p_w(20),21)-usxt(z0_w(20),21);
--   d0_w(21)<=usxt(p_w(21),21)-usxt(z0_w(21),21);
--   d0_w(22)<=usxt(p_w(22),21)-usxt(z0_w(22),21);
--   
--   
--   d1_w(0)<=usxt(p_w(0),21)-usxt(z1_w(0),21);
--   d1_w(1)<=usxt(p_w(1),21)-usxt(z1_w(1),21);
--   d1_w(2)<=usxt(p_w(2),21)-usxt(z1_w(2),21);
--   d1_w(3)<=usxt(p_w(3),21)-usxt(z1_w(3),21);
--   d1_w(4)<=usxt(p_w(4),21)-usxt(z1_w(4),21);
--   d1_w(5)<=usxt(p_w(5),21)-usxt(z1_w(5),21);
--   d1_w(6)<=usxt(p_w(6),21)-usxt(z1_w(6),21);
--   d1_w(7)<=usxt(p_w(7),21)-usxt(z1_w(7),21);
--   d1_w(8)<=usxt(p_w(8),21)-usxt(z1_w(8),21);
--   d1_w(9)<=usxt(p_w(9),21)-usxt(z1_w(9),21);
--   d1_w(10)<=usxt(p_w(10),21)-usxt(z1_w(10),21);
--   d1_w(11)<=usxt(p_w(11),21)-usxt(z1_w(11),21);
--   d1_w(12)<=usxt(p_w(12),21)-usxt(z1_w(12),21);
--   d1_w(13)<=usxt(p_w(13),21)-usxt(z1_w(13),21);
--   d1_w(14)<=usxt(p_w(14),21)-usxt(z1_w(14),21);
--   d1_w(15)<=usxt(p_w(15),21)-usxt(z1_w(15),21);
--   d1_w(16)<=usxt(p_w(16),21)-usxt(z1_w(16),21);
--   d1_w(17)<=usxt(p_w(17),21)-usxt(z1_w(17),21);
--   d1_w(18)<=usxt(p_w(18),21)-usxt(z1_w(18),21);
--   d1_w(19)<=usxt(p_w(19),21)-usxt(z1_w(19),21);
--   d1_w(20)<=usxt(p_w(20),21)-usxt(z1_w(20),21);
--   d1_w(21)<=usxt(p_w(21),21)-usxt(z1_w(21),21);
--   d1_w(22)<=usxt(p_w(22),21)-usxt(z1_w(22),21);
end process;

process(clk,flag1)
  begin
    if flag1 = '1' then 
    if clk'event and clk='1'  then
      s019<=s0(19);
      s119<=s1(19);
      --d012<=d0_w(12);
--      d112<=d1_w(12);
--      d013<=d0_w(13);
--      d113<=d1_w(13);
      --d014<=d0_w(14);
--      d114<=d1_w(14);
--      d015<=d0_w(15);
--      d115<=d1_w(15);
--      d016<=d0_w(16);
--      d116<=d1_w(16);
--      d017<=d0_w(17);
--      d117<=d1_w(17);
--      d018<=d0_w(18);
--      d118<=d1_w(18);
--      d019<=d0_w(19);
--      d119<=d1_w(19);
--      d020<=d0_w(20);
--      d120<=d1_w(20);
--      d021<=d0_w(21);
--      d121<=d1_w(21);
    --  d022<=d0_w(22);
     --  d122<=d1_w(22);
  
     -- flag_f<='1';
    end if;
    end if;
  end process;
  
--  
--   process(clk)
--  begin
--    if clk'event and clk='1'  then
--      --d012<=d0_w(12);
----      d112<=d1_w(12);
----      d013<=d0_w(13);
----      d113<=d1_w(13);
--      --d014<=d0_w(14);
----      d114<=d1_w(14);
----      d015<=d0_w(15);
----      d115<=d1_w(15);
----      d016<=d0_w(16);
----      d116<=d1_w(16);
----      d017<=d0_w(17);
----      d117<=d1_w(17);
----      d018<=d0_w(18);
----      d118<=d1_w(18);
----      d019<=d0_w(19);
----      d119<=d1_w(19);
----      d020<=d0_w(20);
----      d120<=d1_w(20);
----      d021<=d0_w(21);
----      d121<=d1_w(21);
--
--      d122<=d1_w(22);
--     -- flag_f<='1';
--    end if;
--  end process;
--
--process(clk)
--  begin
--    if clk'event and clk='1'  then
--      --d012<=d0_w(12);
----      d112<=d1_w(12);
----      d013<=d0_w(13);
----      d113<=d1_w(13);
--      --d014<=d0_w(14);
----      d114<=d1_w(14);
----      d015<=d0_w(15);
----      d115<=d1_w(15);
----      d016<=d0_w(16);
----      d116<=d1_w(16);
----      d017<=d0_w(17);
----      d117<=d1_w(17);
----      d018<=d0_w(18);
----      d118<=d1_w(18);
----      d019<=d0_w(19);
----      d119<=d1_w(19);
----      d020<=d0_w(20);
----      d120<=d1_w(20);
----      d021<=d0_w(21);
----      d121<=d1_w(21);
--      d0222<=d022;
--      d1222<=d122;
--    end if;
--  end process;
--  
--b1_1:max2_21to1_21bit port map(x1=>d0_w(0),x2=>d0_w(1),y=>s0(0));
--b1_2:max2_21to1_21bit port map(x1=>d0_w(2),x2=>d0_w(3),y=>s0(1));
--b1_3:max2_21to1_21bit port map(x1=>d0_w(4),x2=>d0_w(5),y=>s0(2));
--b1_4:max2_21to1_21bit port map(x1=>d0_w(6),x2=>d0_w(7),y=>s0(3));
--b1_5:max2_21to1_21bit port map(x1=>d0_w(8),x2=>d0_w(9),y=>s0(4));
--b1_6:max2_21to1_21bit port map(x1=>d0_w(10),x2=>d0_w(11),y=>s0(5));
--b1_7:max2_21to1_21bit port map(x1=>d0_w(12),x2=>d0_w(13),y=>s0(6));
--b1_8:max2_21to1_21bit port map(x1=>d0_w(14),x2=>d0_w(15),y=>s0(7));
--b1_9:max2_21to1_21bit port map(x1=>d0_w(16),x2=>d0_w(17),y=>s0(8));
--b1_10:max2_21to1_21bit port map(x1=>d0_w(18),x2=>d0_w(19),y=>s0(9));
--b1_11:max2_21to1_21bit port map(x1=>d0_w(20),x2=>d0_w(21),y=>s0(10));
--b2_1:max2_21to1_21bit port map(x1=>s0(0),x2=>s0(1),y=>s0(11));
--b2_2:max2_21to1_21bit port map(x1=>s0(2),x2=>s0(3),y=>s0(12));
--b2_3:max2_21to1_21bit port map(x1=>s0(4),x2=>s0(5),y=>s0(13));
--b2_4:max2_21to1_21bit port map(x1=>s0(6),x2=>s0(7),y=>s0(14));
--b2_5:max2_21to1_21bit port map(x1=>s0(8),x2=>s0(9),y=>s0(15));
--b2_6:max2_21to1_21bit port map(x1=>s0(10),x2=>d0_w(22),y=>s0(16));
--b3_1:max2_21to1_21bit port map(x1=>s0(11),x2=>s0(12),y=>s0(17));
--b3_2:max2_21to1_21bit port map(x1=>s0(13),x2=>s0(14),y=>s0(18));
--b3_3:max2_21to1_21bit port map(x1=>s0(15),x2=>s0(16),y=>s0(19));
--b4_1:max2_21to1_21bit port map(x1=>s0(17),x2=>s0(18),y=>s0(20));
--b5_1:max2_21to1_21bit port map(x1=>s0(19),x2=>s0(20),y=>t0_w);
s0(0)<=max2_24(d0_w(0),d0_w(1));
s0(1)<=max2_24(d0_w(2),d0_w(3));
s0(2)<=max2_24(d0_w(4),d0_w(5));
s0(3)<=max2_24(d0_w(6),d0_w(7));
s0(4)<=max2_24(d0_w(8),d0_w(9));
s0(5)<=max2_24(d0_w(10),d0_w(11));
s0(6)<=max2_24(d0_w(12),d0_w(13));
s0(7)<=max2_24(d0_w(14),d0_w(15));
s0(8)<=max2_24(d0_w(16),d0_w(17));
s0(9)<=max2_24(d0_w(18),d0_w(19));
s0(10)<=max2_24(d0_w(20),d0_w(21));
--s0(11)<=max2_21(s0(0),s0(1));
--s0(12)<=max2_21(s0(2),s0(3));
--s0(13)<=max2_21(s0(4),s0(5));
--s0(14)<=max2_21(s0(6),s0(7));
--s0(15)<=max2_21(s0(8),s0(9));
--s0(16)<=max2_21(s0(10),d0_w(22));
--    b1_1:max2clk_21 port map(clk=>clk,x1=>d0_w(0),x2=>d0_w(1),y=>s0(0));
--b1_2:max2clk_21 port map(clk=>clk,x1=>d0_w(2),x2=>d0_w(3),y=>s0(1));
--b1_3:max2clk_21 port map(clk=>clk,x1=>d0_w(4),x2=>d0_w(5),y=>s0(2));
--b1_4:max2clk_21 port map(clk=>clk,x1=>d0_w(6),x2=>d0_w(7),y=>s0(3));
--b1_5:max2clk_21 port map(clk=>clk,x1=>d0_w(8),x2=>d0_w(9),y=>s0(4));
--b1_6:max2clk_21 port map(clk=>clk,x1=>d0_w(10),x2=>d0_w(11),y=>s0(5));
--b1_7:max2clk_21 port map(clk=>clk,x1=>d0_w(12),x2=>d0_w(13),y=>s0(6));
--b1_8:max2clk_21 port map(clk=>clk,x1=>d0_w(14),x2=>d0_w(15),y=>s0(7));
--b1_9:max2clk_21 port map(clk=>clk,x1=>d0_w(16),x2=>d0_w(17),y=>s0(8));
--b1_10:max2clk_21 port map(clk=>clk,x1=>d0_w(18),x2=>d0_w(19),y=>s0(9));
--b1_11:max2clk_21 port map(clk=>clk,x1=>d0_w(20),x2=>d0_w(21),y=>s0(10));
b2_1:max2clk_24 port map(clk=>clk,x1=>s0(0),x2=>s0(1),y=>s0(11));
b2_2:max2clk_24 port map(clk=>clk,x1=>s0(2),x2=>s0(3),y=>s0(12));
b2_3:max2clk_24 port map(clk=>clk,x1=>s0(4),x2=>s0(5),y=>s0(13));
b2_4:max2clk_24 port map(clk=>clk,x1=>s0(6),x2=>s0(7),y=>s0(14));
b2_5:max2clk_24 port map(clk=>clk,x1=>s0(8),x2=>s0(9),y=>s0(15));
b2_6:max2clk_24 port map(clk=>clk,x1=>s0(10),x2=>d0_w(22),y=>s0(16));
b3_1:max2clk_24 port map(clk=>clk,x1=>s0(11),x2=>s0(12),y=>s0(17));
b3_2:max2clk_24 port map(clk=>clk,x1=>s0(13),x2=>s0(14),y=>s0(18));
b3_3:max2clk_24 port map(clk=>clk,x1=>s0(15),x2=>s0(16),y=>s0(19));
b4:max2clk_24 port map(clk=>clk,x1=>s0(17),x2=>s0(18),y=>s0(20));
--b5:max2clk_21 port map(clk=>clk,x1=>s0(19),x2=>s0(20),y=>t0_w);
----b2_7:max2clk_21 port map(clk=>clk,x1=>s0(11),x2=>s0(12),y=>s0(17));
--b2_8:max2clk_21 port map(clk=>clk,x1=>s0(13),x2=>s0(14),y=>s0(18));
--b2_9:max2clk_21 port map(clk=>clk,x1=>s0(15),x2=>s0(12),y=>s0(17));
--b2_10:max2clk_21 port map(clk=>clk,x1=>s0(11),x2=>s0(12),y=>s0(17));
--s0(6)<=max2_21(d012,d013);
--s0(7)<=max2_21(d014,d015);
--s0(8)<=max2_21(d016,d017);
--s0(9)<=max2_21(d018,d019);
--s0(10)<=max2_21(d020,d021);
   --s0(11)<=max2_21(s0(0),s0(1));
--s0(12)<=max2_21(s0(2),s0(3));
--s0(13)<=max2_21(s0(4),s0(5));
--s0(14)<=max2_21(s0(6),s0(7));
--s0(15)<=max2_21(s0(8),s0(9));
--s0(16)<=max2_21(s0(10),d022);
 -- s0(17)<=max2_21(s0(11),s0(12));
 -- s0(18)<=max2_21(s0(13),s0(14));
 -- s0(19)<=max2_21(s0(15),s0(16));
-- s0(20)<=max2_21(s0(17),s0(18));
t0_w<=max2_24(s019,s0(20));


--c1_1:max2_21to1_21bit port map(x1=>d1_w(0),x2=>d1_w(1),y=>s1(0));
--c1_2:max2_21to1_21bit port map(x1=>d1_w(2),x2=>d1_w(3),y=>s1(1));
--c1_3:max2_21to1_21bit port map(x1=>d1_w(4),x2=>d1_w(5),y=>s1(2));
--c1_4:max2_21to1_21bit port map(x1=>d1_w(6),x2=>d1_w(7),y=>s1(3));
--c1_5:max2_21to1_21bit port map(x1=>d1_w(8),x2=>d1_w(9),y=>s1(4));
--c1_6:max2_21to1_21bit port map(x1=>d1_w(10),x2=>d1_w(11),y=>s1(5));
--c1_7:max2_21to1_21bit port map(x1=>d1_w(12),x2=>d1_w(13),y=>s1(6));
--c1_8:max2_21to1_21bit port map(x1=>d1_w(14),x2=>d1_w(15),y=>s1(7));
--c1_9:max2_21to1_21bit port map(x1=>d1_w(16),x2=>d1_w(17),y=>s1(8));
--c1_10:max2_21to1_21bit port map(x1=>d1_w(18),x2=>d1_w(19),y=>s1(9));
--c1_11:max2_21to1_21bit port map(x1=>d1_w(20),x2=>d1_w(21),y=>s1(10));
--c2_1:max2_21to1_21bit port map(x1=>s1(0),x2=>s1(1),y=>s1(11));
--c2_2:max2_21to1_21bit port map(x1=>s1(2),x2=>s1(3),y=>s1(12));
--c2_3:max2_21to1_21bit port map(x1=>s1(4),x2=>s1(5),y=>s1(13));
--c2_4:max2_21to1_21bit port map(x1=>s1(6),x2=>s1(7),y=>s1(14));
--c2_5:max2_21to1_21bit port map(x1=>s1(8),x2=>s1(9),y=>s1(15));
--c2_6:max2_21to1_21bit port map(x1=>s1(10),x2=>d1_w(22),y=>s1(16));
--c3_1:max2_21to1_21bit port map(x1=>s1(11),x2=>s1(12),y=>s1(17));
--c3_2:max2_21to1_21bit port map(x1=>s1(13),x2=>s1(14),y=>s1(18));
--c3_3:max2_21to1_21bit port map(x1=>s1(15),x2=>s1(16),y=>s1(19));
--c4_1:max2_21to1_21bit port map(x1=>s1(17),x2=>s1(18),y=>s1(20));
--c5_1:max2_21to1_21bit port map(x1=>s1(19),x2=>s1(20),y=>t1_w);
s1(0)<=max2_24(d1_w(0),d1_w(1));
s1(1)<=max2_24(d1_w(2),d1_w(3));
s1(2)<=max2_24(d1_w(4),d1_w(5));
s1(3)<=max2_24(d1_w(6),d1_w(7));
s1(4)<=max2_24(d1_w(8),d1_w(9));
s1(5)<=max2_24(d1_w(10),d1_w(11));
s1(6)<=max2_24(d1_w(12),d1_w(13));
s1(7)<=max2_24(d1_w(14),d1_w(15));
s1(8)<=max2_24(d1_w(16),d1_w(17));
s1(9)<=max2_24(d1_w(18),d1_w(19));
s1(10)<=max2_24(d1_w(20),d1_w(21));
--s1(11)<=max2_21(s1(0),s1(1));
--s1(12)<=max2_21(s1(2),s1(3));
--s1(13)<=max2_21(s1(4),s1(5));
--s1(14)<=max2_21(s1(6),s1(7));
--s1(15)<=max2_21(s1(8),s1(9));
--s1(16)<=max2_21(s1(10),d1_w(22));
--         c1_1:max2clk_21 port map(clk=>clk,x1=>d1_w(0),x2=>d1_w(1),y=>s1(0));
--c1_2:max2clk_21 port map(clk=>clk,x1=>d1_w(2),x2=>d1_w(3),y=>s1(1));
--c1_3:max2clk_21 port map(clk=>clk,x1=>d1_w(4),x2=>d1_w(5),y=>s1(2));
--c1_4:max2clk_21 port map(clk=>clk,x1=>d1_w(6),x2=>d1_w(7),y=>s1(3));
--c1_5:max2clk_21 port map(clk=>clk,x1=>d1_w(8),x2=>d1_w(9),y=>s1(4));
--c1_6:max2clk_21 port map(clk=>clk,x1=>d1_w(10),x2=>d1_w(11),y=>s1(5));
--c1_7:max2clk_21 port map(clk=>clk,x1=>d1_w(12),x2=>d1_w(13),y=>s1(6));
--c1_8:max2clk_21 port map(clk=>clk,x1=>d1_w(14),x2=>d1_w(15),y=>s1(7));
--c1_9:max2clk_21 port map(clk=>clk,x1=>d1_w(16),x2=>d1_w(17),y=>s1(8));
--c1_10:max2clk_21 port map(clk=>clk,x1=>d1_w(18),x2=>d1_w(19),y=>s1(9));
--c1_11:max2clk_21 port map(clk=>clk,x1=>d1_w(20),x2=>d1_w(21),y=>s1(10));
c2_1:max2clk_24 port map(clk=>clk,x1=>s1(0),x2=>s1(1),y=>s1(11));
c2_2:max2clk_24 port map(clk=>clk,x1=>s1(2),x2=>s1(3),y=>s1(12));
c2_3:max2clk_24 port map(clk=>clk,x1=>s1(4),x2=>s1(5),y=>s1(13));
c2_4:max2clk_24 port map(clk=>clk,x1=>s1(6),x2=>s1(7),y=>s1(14));
c2_5:max2clk_24 port map(clk=>clk,x1=>s1(8),x2=>s1(9),y=>s1(15));
c2_6:max2clk_24 port map(clk=>clk,x1=>s1(10),x2=>d1_w(22),y=>s1(16));
c3_1:max2clk_24 port map(clk=>clk,x1=>s1(11),x2=>s1(12),y=>s1(17));
c3_2:max2clk_24 port map(clk=>clk,x1=>s1(13),x2=>s1(14),y=>s1(18));
c3_3:max2clk_24 port map(clk=>clk,x1=>s1(15),x2=>s1(16),y=>s1(19));
c4:max2clk_24 port map(clk=>clk,x1=>s1(17),x2=>s1(18),y=>s1(20));
--c5:max2clk_21 port map(clk=>clk,x1=>s1(19),x2=>s1(20),y=>t1_w);
--s1(6)<=max2_21(d112,d113);
--s1(7)<=max2_21(d114,d115);
--s1(8)<=max2_21(d116,d117);
--s1(9)<=max2_21(d118,d119);
--s1(10)<=max2_21(d120,d121);
     --  s1(11)<=max2_21(s1(0),s1(1));
--s1(12)<=max2_21(s1(2),s1(3));
--s1(13)<=max2_21(s1(4),s1(5));
--s1(14)<=max2_21(s1(6),s1(7));
--s1(15)<=max2_21(s1(8),s1(9));
--s1(16)<=max2_21(s1(10),d122);
--s1(17)<=max2_21(s1(11),s1(12));
--s1(18)<=max2_21(s1(13),s1(14));
--s1(19)<=max2_21(s1(15),s1(16));
--s1(20)<=max2_21(s1(17),s1(18));
t1_w<=max2_24(s119,s1(20));

--process(clk)
--  begin
--    if clk'event and clk='1' then
--      res<=t0_w-t1_w;
--    end if;
--  end process;
--
--end beh;
--
--







 
process(clk,flag,flag1)

  variable s2: std_ulogic_vector(24 downto 0);
  
  
  begin

  if clk'event and clk='1' then
    if flag='1' then
      if flag1='1'  then
          s2:=usxt(t1_w,25)-usxt(t0_w,25);
			 if s2(24)='0'  then
			    if (s2(23) or s2(22) or s2(21) or s2(20) or s2(19) or s2(18) or s2(17) or s2(16) or s2(15)or s2(14))='1'  then
			       s_w<=s2(24)&("011111111111111");
			    else 
			       s_w<=s2(24)&s2(14 downto 0);
			    end if;
			 else 
			    if (s2(23) and s2(22) and s2(21) and s2(20) and s2(19) and s2(18) and s2(17) and s2(16) and s2(15)and s2(14))='0'  then
			       s_w<=s2(24)&("100000000000001");
			    else 
			       s_w<=s2(24)&s2(14 downto 0);
			    end if;
			 end if;
      else
       s_w<=  (others => '0'  );
      end if;
   else
     s_w<=(others => '0');
   end if;
  end if;
end process;



  
  



end beh;

